1. Technical Field
The present disclosure relates to the manufacturing of integrated circuits on a semiconductor wafer, and more particularly to a method for manufacturing a bipolar transistor compatible with CMOS (Complementary Metal Oxide Semiconductor) manufacturing methods.
2. Description of the Related Art
Generally, the formation of vertical bipolar transistors in a CMOS circuit employs a significant number of resists and additional manufacturing steps. These additional steps relate in particular to forming doped zones to produce the emitter, the base and the collector of the bipolar transistor at different depths in the semiconductor wafer. These steps are generally not useful to form CMOS transistors that are usually produced on the surface of the wafer.
Certain techniques of forming a bipolar transistor use the formation of isolated wells that are produced for the CMOS transistors. The bipolar transistors obtained using these techniques generally have insufficient performances, in particular in terms of gain and frequency resistance, for most applications. The steps of forming these wells are indeed optimized for the formation of CMOS transistors, but not for the formation of bipolar transistors.
One well-known method also involves producing in CMOS circuits bipolar transistors which can achieve a higher gain, in the order of 100, and a frequency resistance of a few tens of GHz. FIG. 1 thus represents a cross-section of an example of a PNP-type bipolar transistor formed in a semiconductor wafer. The bipolar transistor comprises a base BW formed by an N-doped well, an N-doped isolating well NISO, produced deep down, and a collector produced by several layers of different types of doping, formed between the base well BW and the isolating well. In this example, the collector comprises a P+-doped well PPW, formed above the well NISO, and another P-doped well PW, formed between the wells PPW and BW. The emitter of the bipolar transistor is formed by a P-doped layer of polysilicon ET, deposited on the base well BW. The sides of the emitter ET are protected by isolating spacers SP. A base contact is produced by an N+-doped zone BD formed in the base well BW around the emitter ET, and topped by a connecting metal layer. A collector contact CPD is formed by a P+-doped region, isolated from the base well BW by means of an isolating trench STI. The collector contact CPD is formed in a P-doped well CLW, ensuring the electrical link between the collector contact CPD and the well PPW. The well NISO is biased by means of a well contact formed by an N+-doped zone SPD, electrically linked to the layer NISO by two N+-doped wells SLW and SNW.
Unlike CMOS transistors, the manufacturing of this transistor forms a significant number of doped wells, and thus employs a large number of resists and doping steps. In addition, this transistor also occupies a significant wafer surface area.